PACKAGING CONSTRUCTION FOR VERY LARGE SCALE INTEGRATED-CIRCUIT CHIPS

Abstract

A novel IC chip packaging construction in which the chip package materials are selected such that their thermal linear expansion curves are closely matched over the full operating temperature range of the IC chip. The IC chip packaging construction includes a metal base and cover for enclosing the IC chip and a pair of insulating frames for hermetically sealing the IC chip in the chip package. A plurality of input/output leads make electrical connections with the IC chip through fine wires that are soldered to the leads and to contact areas on the IC chip. The metal base and cover and the input/output leads are fabricated from copper and the insulating frames are fabricated from Fotoceram® 160, which has a thermal linear expansion curve that closely matches that of copper over the full operating temperature range of the chip. Accordingly, the problems of differential expansion rates due to temperature variations for wafer size or very large scale IC chips are greatly minimized.

Source: Google Patents

35 USC §181 Secrecy Order

Inventor

• 1ROBERT SMOLLEY