COHERENT INTEGRATOR

Abstract

A method and circuit for performing coherent integration on a signal outputrom a conventional signal processing circuit's detector/averager is presented. The post-processing coherent integrator is designed to be inserted in a conventional signal processing circuit between the detector/averager circuit and the threshold detector circuit. A digital form of the post processing coherent integrator comprises a sample-and-hold circuit to receive a signal output from the detector averager of the conventional signal processing circuit, an analog-to-digital converter, a delay and multiplier circuit, a memory circuit for storing weighting constants, a summer circuit, and an output to a conventional signal processing system's threshold detector and display. The delay and multiplier circuit operates on N samples of the input signal and causes each sample to be delayed sequentially over a delay ranging from a lower limit of 0 delay up to an upper limit of (N-1)T delay where T is a preselected interval of time and each delay is some different integral multiple of T. Following the delay of each sample, each sample is then multiplied by a predetermined weighting constant. The set of delayed and weighted sample signals are then summed to form a coherent output signal containing information from each delayed and weighted signal sample. This output signal is then fed to the conventional signal processing system's threshold detector and display. An alternative to this integrator incorporates means for real time adaptive setting of the weighting constants. An analog form of the post-processing coherent integrator comprises N-delay lines which function as the delay portion of the above delay and multiplier circuit. In addition, following each delay line is a variable resistor which is preset at a predetermined value to attenuate the signal from the delay lines thereby performing effectively the weighting process on these signals. Following this, all the signals are summed and amplified to again provide an output signal containing information from each delayed and weighted signal sample.

Source: Google Patents

35 USC §181 Secrecy Order

Inventor

• 1ALDO G. DI LORETO

Sensitive facility: Arlington VA (defense contractors)

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