LONG SEQUENCE CORRELATION COPROCESSOR

Abstract

A long sequence correlation coprocessor LSCC accelerates the bitwise corrtion of arbitrarily long digital sequences by calculating in parallel the correlation score for 16, for example, adjacent bit alignments between two binary sequences. The LSCC integrated circuit is incorporated into a computer system with memory storage buffers and a separate general purpose computer processor which serves as its controller. Each of the LSCC's set of sequential counters simultaneously tallies a separate correlation coefficient. During each LSCC clock cycle, counter enable logic associated with each counter compares one bit of a first sequence with one bit of a second sequence to increment the counter if the bits are the same. A shift register assures that the same bit of the first sequence is simultaneously compared to different bits of the second sequence to simultaneously calculate the correlation coefficient by the different counters to represent different alignments of the two sequences. Two sequence input elements, each with a control block, present the sequence bits serially to this shift register and the count enable logic associated with the sequential counters. Two (or some other number of) data receivers accept externally clocked serial data streams, divide them into computer words, and make them available for the external computer processor to transfer to external memory storage buffers. The external computer processor controls the LSCC's correlation process by writing appropriate control parameters to the LSCC's control registers; by writing the length of the sequences to be correlated to the LSCC's length register; by coordinating the flow of the data streams from the LSCC's data receivers to the memory storage buffers; by coordinating the flow of the words of data from the memory storage buffers to the LSCC's sequence input elements as required; and by reading the correlation coefficients from the sequential counters upon completion of each full correlation calculation.

Source: Google Patents

35 USC §181 Secrecy Order

Inventor

• 1DOUGLAS W. GAGE

Sensitive facility: San Diego CA (SAIC/General Dynamics)