COHERENT SIDE LOBE CANCELER

Abstract

The elimination of jamming signals from received radar signals is conventionally accomplished by side lobe cancellation techniques. Large interfering signals caused either by clutter or other sources, however, can cause intolerable degradation of coherent side lobe cancellation (CSLC) systems. In the present invention an inhibit signal is used to open the input to the coherent side lobe cancellation error sensing circuits thus preventing large signals from entering the coherent side lobe cancellation loop. Large signals entering coherent side lobe cancellation loops give rise to erroneous transients in the output. The invention effects storage of previously sensed error signals so as to continue jammer cancellation until new data become available to update the error signals. The inhibit signal is generated by a combination of coherent side lobe cancellation sensing circuits and logic control circuits that determine when an inhibit signal should be generated. When an inhibit signal is not present, the coherent side lobe cancellation loop operates in its normal fashion. During intervals when excessive clutter or signal is present on the main channel, an inhibit signal is generated causing the occurrence of two actions in the coherent side lobe cancellation loop. First, the inhibit signal opens a switch at the output of the correlation mixer so that no input is accepted into the coherent side lobe cancellation loop for a time interval, thereby preventing the large signal from disturbing the loop operation. Second and simultaneously, the inhibit signal causes a sample-and-hold circuit to sample the loop filter output thereby preventing the loops from relaxing during this time interval.

Source: Google Patents

35 USC §181 Secrecy Order

Inventor

• 1NOROL T. EVANS

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