LOCK MEANS AND TV SYNC FOR AIR-TO-SURFACE-MISSILE

Abstract

1. A digital code synchronization locking means comprising: means to receive a first digital code sequence; means to generate a second digital code sequence substantially similar to id first sequence, said means to generate said (second) digital code sequence including: a shift register having an output from a predetermined stage thereof; a feedback logic matrix connected to said shift register for generating said second digital code sequence; a binary pulse counter, the last stage of which provides a reset pulse to all the stages of said shift register; means to detect drift from synchronization of said second code sequence with said first code sequence one stage before said predetermined stage and one stage after said predetermined stage; a clock oscillator providing clock pulses to all stages of said shift register and to the first stage of said binary counter; and an oscillator control connected to said clock oscillator and responsive to said means to detect drift for advancing the rate of said clock oscillator upon correlation of said first code sequence with said one stage before said predetermined stage and retarding the rate of said clock oscillator upon correlation of said first code sequence with said one stage after said predetermined stage, whereby said second code sequence is maintained in synchronization with said first code sequence.

Source: Google Patents

35 USC §181 Secrecy Order

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