FABRICATION OF INTEGRATED CIRCUITS INCORPORATING IN-PROCESS AVOIDANCE OF CIRCUIT-KILLER PARTICLES

Abstract

In the manufacture of an integrated circuit, steps of the process are dynamically augmented, so as to fabricate the integrated circuit at wafer locations which avoid the presence of circuit-killing particulates. During the respective steps of fabrication, the components employed in the process are scanned to locate and identify particulates. This information is compared with a previously defined component/interconnect layout to determine whether the particulates reside at locations that will not detrimentally impact the completed circuit or whether further processing will incorporate the defect into the circuit and render it effectively useless. In this latter circumstance the intended geometries of the circuit are modified, so as to effectively rearrange or shift prescribed components (e.g. semiconductor regions, contact apertures, interconnect tracks) to a location of the wafer which are not coincident with the location of the particulates.

Source: Google Patents

35 USC §181 Secrecy Order

Inventor

• 1JAMES M. MADER

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