CACHE MEMORY AND PRE-PROCESSOR
Assignee
JOHNS HOPKINS UNIVERSITY, THE
Filed
May 25, 1984
Granted
Nov 29, 1988
Location
COLUMBIA MD US
Abstract
The invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a memory dedicated to the host microprocessor. For example, the cache memory can be reconfigured from a 2K byte by 16-bit space during the acquisition mode to a 4K byte ×8-bit space during the retrieval mode, wherein the high and low bytes of the previously defined 16-bit words are interleaved.
Source: Google Patents
35 USC §181 Secrecy Order
Imposed
Nov 23, 1984
Rescinded
Jul 27, 1988
Duration
3 years, 8 months
Inventor
- 1WAYNE I. STERNBERGER
Record Details
- Patent number
- US 4788656
- Application
- 06614226
- Aerospace match
- No
- Dataset source
- 35 USC §181 SO records