PARTITIONED SCAN-TESTING SYSTEM
Assignee
TEXAS INSTRUMENTS INCORPORATED, 13500 NORTH CENTRAL EXPRESSWAY, DALLAS, TEXAS, 75231, A CORP OF DELAWARE
Filed
Oct 23, 1985
Granted
Dec 1, 1987
Location
HOUSTON TX US
Abstract
A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.
Source: Google Patents
35 USC §181 Secrecy Order
Imposed
Mar 26, 1986
Rescinded
Oct 21, 1986
Duration
6 months
Inventor
- 1JEFFREY D. BELLAY
Record Details
- Patent number
- US 4710931
- Application
- 06790543
- Aerospace match
- No
- Dataset source
- 35 USC §181 SO records